Easy-To-Use SystemVerilog Parser
Project description
Easy-To-Use SystemVerilog Parser
Features
- Extract Port Lists
- Extract Parameters
- Extract Submodule Instances
ifdefsupport (planned)- Standards:
IEEE 1800-2009 SystemVerilog
Limitations
- No Syntax Checks - Source Code files must be syntactically correct
- No Full Parser - This parser intends to be simple and just extract some information from the source code. Fast and easy.
Installation
Installing it is pretty easy:
pip install sv-simpleparser
Project details
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