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Consider using release 0.7.1 instead.
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PeakRDL-BusDecoder

Generate a SystemVerilog bus decoder from SystemRDL that splits CPU interface signals to multiple sub-address spaces. This tool is designed for creating hierarchical register address maps by decoding bus transactions and routing them to the appropriate child address maps.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-BusDecoder Documentation for more details

Project links

Data verified by PyPI on Jul 8, 2026
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  • Yanked:
Newer release available (0.7.1)

1 maintainer

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Credits

Author: Arnav Sacheti

GitHub Statistics

Data verified by PyPI on Jul 8, 2026
The GitHub source repository was provided by the project maintainers and verified by PyPI at the time of upload. Stars, forks, and open issues/PRs are derived from that repository and have not been independently verified.

License

GNU Lesser General Public License v3 (LGPLv3) (LGPLv3)

Requires

Python >=3.10

Provides Extra

cli

Tags

SystemRDL PeakRDL bus decoder address decoder hierarchical addressing compiler tool registers generator Verilog SystemVerilog register abstraction layer FPGA ASIC

Classifiers

Report project as malware

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