Compile SystemRDL into a SystemVerilog control/status register (CSR) block

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License: GNU General Public License v3 (GPLv3) (GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Copyright (C) 2007 Free Software Foundation, Inc...)

Author: Alex Mykyta

Tags SystemRDL, PeakRDL, CSR, compiler, tool, registers, generator, Verilog, SystemVerilog, register abstraction layer, FPGA, ASIC

Requires: Python >=3.6

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PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details

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Meta

License: GNU General Public License v3 (GPLv3) (GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Copyright (C) 2007 Free Software Foundation, Inc...)

Author: Alex Mykyta

Tags SystemRDL, PeakRDL, CSR, compiler, tool, registers, generator, Verilog, SystemVerilog, register abstraction layer, FPGA, ASIC

Requires: Python >=3.6

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